Verilog: Write a testbench that exhaustively test the following module 2(bi-t)comparator

Please use "for ( ) end" and interger i

module twobitComparator CA, B, IGT, IEQ,ILT,OGRE,OEQU,OLES) F input [1:0] A, B input IEQ, IGT,ILT output reg OGRE ,OEQU,OLES reg check; always a CA, B,IGT,ILT,IEQ) begin check IEQ. II IEQ. l I IGT ILT OGRE IEQ? CA B 1 0) IGT OLES IEQ A