VHDL 4bit counter counts : 14, 12, 10, 8, 6, 4, 2, 0, 1, 3, 5, 7, 9, 11, 13, 15

my code did counts from 14-0 but not from 0-15

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_arith.all;

-

entity mycounter is

port ( clock, resetn, E: in std_logic;

Q: out std_logic_vector (3 downto 0));

end mycounter;

architecture Behavioral of mycounter is

signal Qt: integer range 0 to 15;

begin

process (resetn, clock, E)

begin

if resetn = '0' then

Qt <= 0;

elsif (clock'event and clock = '1') then

if E = '1' then

if Qt = 0 then

Qt <= 14;

else

Qt <= Qt -2;

end if;

elsif E='1' then

elsif Qt = 15 then

Qt <= 0;

else

Qt <= Qt + 2;

end if;

end if;

end process;

Q <= conv_std_logic_vector(Qt,4);

end Behavioral;