VHDL CODE in MODELSIM

In this lab assignment, you will develop the VHDL model for an elementary microprocessor of your own that can 'execute' the following instructions: Bit-wise AND, Bit-wise OR, Bit-wise EX-OR, Addition (full addition of 1-bit numbers, with two outputs sum and cout), Subtraction (full-subtraction of 1-bit numbers, with two outputs diff and bout), and Bit-wise complement. Within the processor, each of these instructions is represented as a code word or command, known as opcode. The user provides the data and the opcode as inputs to the processor and, depending on the opcode specified, the appropriate output or outputs should appear on the output side of the processor In this elementary processor, all the operands are 1-bit wide. The addition and subtraction instructions work with three operands, X, Y and Z. The bit-wise complement instruction performs the bit-wise complement operation on Y. The remaining instructions work with the two operands X and Y. (For example, if X-O and Y-1, the results of the Bit-wise AND and the Bitwise OR operations will be , and '1', respectively) Write and simulate the VHDL model of this processor using concurrent signal assignment statements (examples: simple signal assignment, conditional signal assignment and selected signal assignment). Test each opcode case to ensure that the model is accurate by examining the waveforms on the input and output signals Use the following delay specifications: Each individual logic gate in the design (including inverter) has a propagation delay of 2 ns .For the adder and subtractor logic blocks, the maximum delay per block is 6 ns . The maximum overall delay allowed for the processor to process any instruction is 12 ns Compile your program using ModelSim. Generate a sequence of inputs that you can use to verify that the model is functioning correctly. Run the simulation and check the trace to determine correctness