VHDL help please (complier VHDL 2018)

1. (25) Using the sn74163 VHDL model as a guide (you can find it in the Chapter2_examples workspace), create a behavioral model for the sn74190 counter. See the data sheet in this folder to learn exactly how the sn74190 works. Create your test bench by first using the test bench tool. Structure your test bench to use two processes without sensitivity lists. The first process is a clock process where the clock is enabled by a Boolean signal simulation Active. The second process will generate the inputs to the counter and verify the counter outputs are correct. Once all inputs are provided, the second process turns off simulationActive. As a minimum, your test should demonstrate (1) loading one or more values, (2) count up through the entire range of values. Name this design part1 Comments on the sn74190 datasheet The sn74190 is an example of a medium scale integrated circuit first introduced in 1972. In those days, engineers used the datasheet, schematics (page 3 of the datasheet) and timing diagrams (page 5 of the datasheet) to characterized a device's behavior, function, and performance. The remainder of the datasheet gives the electrical and performance characteristics (pages 4-10). Interestingly, the datasheet also includes information on how the device was tested (pages 11-14). A careful read of the datasheet gives you the information you need to create your VHDL model. Note that the sn74190 is a synchronous reversible up/down decade counter. Synchronous means that the flip-flops are updated synchronous with a clock edge. An up/down counter implies the counter can count up or down. Reversible implies you can change the direction of the count at any time. For example, if you are counting up, you can change the count direction to count down. A decade counter is a BCD counter. The first page of the datasheet gives the pinout for the device. The following table gives a summary of the pins: PI Pin Description n Name 1 B D input for QE 2Q 22 counter bit 3 Qu 2 counter bit 4 CTEN Active low count enable 5 DU Count down when 1 up when 6 QC 2' counter bit 7 Q. 2 counter bit 8 GND Circuit ground 9 D D input for Qu 10 C D input for QC 11 LOAD Active low load 12 MAX/MIN One when counter is at its maximal when counting up or minimal value when counting down 13 RCO Active low ripple carry out 14 CLK Clock input 15 A D input for QA 16 VCC Circuit power input Testing Tutorial Testing digital systems can be challenging and this assignment only serves as an introduction. Tests usually take on one of three forms: (1) Functional, (2) Performance, and (3) Fault. Sometimes these are different phases of a single overall test strategy. Functional Testing In functional testing, the goal is to confirm all aspects of the design function as desired. For the sn74162, a functional test would of course include a verification that the counter works, but the test must also include accessory functions, such as reset, load and enable. Furthermore, the test can also included shifting between the different functions to confirm the control circuitry works as desired. Performance Testing In performance testing, you verify that the implementation either meets the desired performance goal or determines the level of performance that an implementation attains. This assignment does not address performance testing because because it is implementation dependent. Fault Testing The context for fault testing is to imagine that you are receiving parts that have just been manufactured. You are working under the assumption that the design is correct, but manufacturing defects may be present. A common fault model is to assume an input is permanently stuck at a particular logic value for example, the enable signal may be stuck in an "on" position. This particular part will count just fine but will be impossible to reset and a series of tests must be designed in order to confirm the part is defect free. This assignment does not address fault testing because it is implementation dependent. 1. (25) Using the sn74163 VHDL model as a guide (you can find it in the Chapter2_examples workspace), create a behavioral model for the sn74190 counter. See the data sheet in this folder to learn exactly how the sn74190 works. Create your test bench by first using the test bench tool. Structure your test bench to use two processes without sensitivity lists. The first process is a clock process where the clock is enabled by a Boolean signal simulation Active. The second process will generate the inputs to the counter and verify the counter outputs are correct. Once all inputs are provided, the second process turns off simulationActive. As a minimum, your test should demonstrate (1) loading one or more values, (2) count up through the entire range of values. Name this design part1 Comments on the sn74190 datasheet The sn74190 is an example of a medium scale integrated circuit first introduced in 1972. In those days, engineers used the datasheet, schematics (page 3 of the datasheet) and timing diagrams (page 5 of the datasheet) to characterized a device's behavior, function, and performance. The remainder of the datasheet gives the electrical and performance characteristics (pages 4-10). Interestingly, the datasheet also includes information on how the device was tested (pages 11-14). A careful read of the datasheet gives you the information you need to create your VHDL model. Note that the sn74190 is a synchronous reversible up/down decade counter. Synchronous means that the flip-flops are updated synchronous with a clock edge. An up/down counter implies the counter can count up or down. Reversible implies you can change the direction of the count at any time. For example, if you are counting up, you can change the count direction to count down. A decade counter is a BCD counter. The first page of the datasheet gives the pinout for the device. The following table gives a summary of the pins: PI Pin Description n Name 1 B D input for QE 2Q 22 counter bit 3 Qu 2 counter bit 4 CTEN Active low count enable 5 DU Count down when 1 up when 6 QC 2' counter bit 7 Q. 2 counter bit 8 GND Circuit ground 9 D D input for Qu 10 C D input for QC 11 LOAD Active low load 12 MAX/MIN One when counter is at its maximal when counting up or minimal value when counting down 13 RCO Active low ripple carry out 14 CLK Clock input 15 A D input for QA 16 VCC Circuit power input Testing Tutorial Testing digital systems can be challenging and this assignment only serves as an introduction. Tests usually take on one of three forms: (1) Functional, (2) Performance, and (3) Fault. Sometimes these are different phases of a single overall test strategy. Functional Testing In functional testing, the goal is to confirm all aspects of the design function as desired. For the sn74162, a functional test would of course include a verification that the counter works, but the test must also include accessory functions, such as reset, load and enable. Furthermore, the test can also included shifting between the different functions to confirm the control circuitry works as desired. Performance Testing In performance testing, you verify that the implementation either meets the desired performance goal or determines the level of performance that an implementation attains. This assignment does not address performance testing because because it is implementation dependent. Fault Testing The context for fault testing is to imagine that you are receiving parts that have just been manufactured. You are working under the assumption that the design is correct, but manufacturing defects may be present. A common fault model is to assume an input is permanently stuck at a particular logic value for example, the enable signal may be stuck in an "on" position. This particular part will count just fine but will be impossible to reset and a series of tests must be designed in order to confirm the part is defect free. This assignment does not address fault testing because it is implementation dependent