warn

Check that the inputs for the individual $D$ flip$-$flops are in the correct order. From top to bottom, they should be $clk,D,$ en$.$ If you used the template file provided and didn't add or delete any inputs, you should be fine.

info

This register component is almost identical with the register component in the Digital component library. The only difference is that the Digital registers are always initialised to zero, whereas your register starts with a random value $($it just depends on the initial state of all the SR latches at start$-$up time$).$

Counter #

push

Open the file counter $.$dig. Design a circuit that increments a register each clock cycle. If the ld $($short for load$)$ signal is HIGH then load the value from the input $D$ instead. Verify your design with the tests provided. Ensure that you have pushed your work when finished.

Please draw the circuit!