We are to make a 2-D array that outputs the colors in the code referenced IN VHDL using the arty S7 Board:

If it makes it easier, here's my discord to talk with and if you have any more questions: LegitMidget12#4983

Also the code referenced below is the sample code given to use for this lab:

If you add my discord, it would make it easier to communicate and paste the sample code shown and allows for my entire group to easily communicate back to the person who would so kindly answer this question we've been stuck on forever.

In this lab you will need to create two different screen resolutions with different grid sizes This will be the start of your tile-map. Next lab we add the memory and sprites 320x240 . Create grid of 40x30 Make each grid tile a different color You want each tile to have a way to index Using the pixel_x and pixel_y you need to be able to index which tile in the tile-map 0 1 3 2 6 7 4 8 5 9 13 10 11 12 14 15 Architecture Constant cblue : std_logic_vector(2 downto 0) := "100"; . Constant cgreen : std_logic_vector(2 downto 0) := "010"; Type tile_map is array(0 to 119) of std_logic_vector(2 downto 0); Signal grid_map : tile_map := (cblue, cred, cgreen, ... ); - Signal mapindex: std_logic_vector(7 downto 0); begin Mapindex clk50mhz, reset=>reset, hsync=>hsync, vsync=>vsync, video_on=>video_on, p_tick=>open, pixel_x=>pixel_x, pixel_y=>pixel_y); --You need to make a 50mhk clock divider and set to signal clk50mhz --you need to find the downconvert new pixel x and y --using you new pixel x and y you need to find the tile row and col --using the tile row and col access the array to read the color rgb buffer process (clk100MHZ, reset) begin if reset='1' then rgb_reg '0'); V_sync_reg '0'; h_sync_reg ''; elsif (clk'event and clk='1') then mod2_reg =(HD+HF)) --656 and (h_count reg=(VD+VF)) --490 and (v_count_reg (VD+VF+VR-1)) else -- 491 O'; -- video on/off video_on clk50mhz, reset=>reset, hsync=>hsync, vsync=>vsync, video_on=>video_on, p_tick=>open, pixel_x=>pixel_x, pixel_y=>pixel_y); --You need to make a 50mhk clock divider and set to signal clk50mhz --you need to find the downconvert new pixel x and y --using you new pixel x and y you need to find the tile row and col --using the tile row and col access the array to read the color rgb buffer process (clk100MHZ, reset) begin if reset='1' then rgb_reg '0'); V_sync_reg '0'; h_sync_reg ''; elsif (clk'event and clk='1') then mod2_reg =(HD+HF)) --656 and (h_count reg=(VD+VF)) --490 and (v_count_reg (VD+VF+VR-1)) else -- 491 O'; -- video on/off video_on