We have a 5-stage pipeline: IF instruction fetch ID instruction decode and read registers EX execute instruction or calculate address MEM access memory WB write results to registers

For each of the following blocks of code, (i) determine if there are any pipeline hazards and, if so, what type is each (data hazard or control hazard). Support this with a diagram showing the instructions moving through the pipeline. (ii) if there are pipeline hazards, for how many stages would the pipeline stall? (iii) if there are pipeline hazards, reorder the code to avoid them without introducing new hazards while still accomplishing the same result. (iv) note that there could be more than one hazard in a block of code; deal with all of them.

(a) ADD R1, R2, R3 ADD R4, R5, R6 STR R1, [R8] STR R5, [R8, #4] STR R6, [R8, #8] (b) LDR R1, [R2] ADD R2, R2, #4 LDR R3, [R2] ADD R4, R1, R7 SUB R5, R6, R7 ORR R8, R6, R7 EOR R9, R6, R7