We have a total memory capacity of $4$ Mbytes utilising $128$ Kbyte SRAM chips. To allocate this memory to the smallest address space, provide the array configuration of the chips on the memory board displaying all necessary input and output signals. Then, illustrate how the Memory Address Register $($MAR$)$ and Memory Buffer Register $($MBR$)$ are organised and should support both byte and $16-$bit word access. The Memory Address Register $($MAR$)$ is responsible for holding the memory address being accessed, while the Memory Buffer Register $($MBR$)$ stores the data being read from or written to memory. Follow the steps for answering.

Step $1$: Determine the number of SRAM chips required:

Number of SRAM chips required $=$ Total Capacity of Memory $\frac{?}{?}$ Size of each SRAM chip

Step $2$: Organize the SRAM chips in an array configuration:

Step $3$: Assign Input and Output Signals:

Address Lines:

Data Lines:

Byte Enable $($BE$0,$ BE$1)$:

Read Enable $($RD$)$: Signal to enable reading from memory.

Write Enable $($WR$)$: Signal to enable writing to memory.

Output Enable $($OE$)$: Signal to enable the output buffer.

Chip Enable $($CE$0-$CE$31)$:

Step $4$: Organization of Memory Address Register $($MAR$)$ and Memory Buffer Register $($MBR$)$:

Memory Address Register $($MAR$)$:

Memory Buffer Register $($MBR$)$:

Note: The connection of control signals $($RD$,$ WR$,$ OE$,$ BE$0,$ BE$1,$ CE$0-$CE$31)$ to various control and timing elements will depend on the specific design and implementation of the memory system.