We have been learning about State$-$Machines. For this demonstration problem you will go through the complete design process from design specification to writing Verilog code. It is possible to test this module using our FPGA. The easiest way to test the FPGA is to use the pushbutton$\_$clk module and use the pushbutton as a clk and sw$[0]$ as X$.$ This will give you time to think about what you want to test.

Task

Design a State Machine that has two inputs $($X and RESET$),$ and one output $($EDGE$).$ EDGE is asserted if a transition is detected on X$.$ This means EDGE$=1$ if X is different than it was the last clock tick. RESET is an asynchronous reset signal.

It is possible to test this module on your FPGA. You will need a really slow clock, so I recommend using the pushbutton$\_$clk module that is in the Verilog Sample Files on Moodle.

You are expected to show all pieces of the design process. Design this state machine using a state table, state diagram, or ASM chart. Demonstrate and discuss all the design steps. Provide details about your process.

Use the parameter statement to assign your state variables in your Verilog code.

Deliverables

This design will be assessed as a demonstration problem. You are required to provide a written report following the Demonstration Problems guidelines in the Grading Policy.

Include:

Describe and Discuss all steps taken in the design. This includes but is not limited to:

Development of State Table, Diagram, or ASM chart

Discuss the process you went through to produce this visualization

State Assignments

Coding process

Final Verilog code for all modules $($xdc code is not required$)$

If you did testing, explain your results.