We need to create 4 differerent moduels. State Machine Module, Inventory Module, Display module and a modue to integrate.The assignment needs to be done in verilog and used in Module Sim

Description

In this project we will design a snack vending machine. The vending machine has four products for sale: potato chips, candy bar, canned soda, and cookies. Then vending machine is restocked each morning. The following table lists the price and the restock quantity of each item.

Product	Item Code	Price	Restock Quantity
Potato Chips	A2	$1.25	5
Candy Bar	B3	$1.00	4
Soda	D5	$2.25	3
cookies	E8	$0.75	3

Theory of Operation

The vending machine only accepts one-dollar bills and quarters. The vending machine dispenses change in quarters only. The vending machine keeps up with product inventory.

The following use case scenarios describe the behavior of the vending machine:

1. The user wants pricing information for a specific product. In this scenario the user inputs the item code and the vending machine displays the price for five seconds. After five seconds has elapsed the user may request another items price. If an item is currently out-of-stock, its price is not displayed: instead a special out-of-stock message is displayed.

2. The user wishes to purchase an item. The user firsts provides the item code. The vending machine displays the price for five seconds. Before five seconds elapses the user begins inserting money. If the user does not begin to insert money within five seconds, the vending machine assumes the user only wanted pricing and goes back to being inactive.

Once a user inserts enough money for the current selected item, the vending machine dispenses the item. If the user is owed change, the vending machine then dispenses change. At any time after inserting money, but before inserting all necessary money for the selected item, the user may press the refund button to get all their money back.

System Inputs

Reset is asserted whenever switch S9 is in the on state (active high).

To select an item the user (1st) specifies the two hex code using the eight switches (S8_5 and S3_0) and (2nd) depressing the start button B0.

Pressing button B2 represents the user inserting a one-dollar bill.

Pressing button B1 represents the user inserting a quarter.

Pressing button B3 issues a refund for any money currently added that has not reached the total needed for the current item.

System Outputs

The six 7-segment displays (three groups of two) are used to provide feedback to the user. We will refer to the individual displays as display0 to display5 with display0 being the rightmost when looking at the board as shown in Figure 1.

1. Whenever the vending machine is inactive (no current user input), the five rightmost displays collectively output the word HELLO.

2. The price of an item is displayed to the user on the three rightmost displays in the format X.XX. The two leftmost displays output the current items code. Unless the user begins inserting money, the price must be displayed for five seconds.

3. Once a user begins adding money, the current total amount added is displayed on the three rightmost displays in the format X.XX. The leftmost display outputs the letter E to signify Entered

4. Whenever money is being dispensed back to the user, the leftmost display outputs the letter C to signify Change. The rightmost display outputs the total amount being dispensed. The user must be presented with this display for five seconds.

5. To signify an out-of-stock item each of the six displays output the character -. The user must be presented with this display for three seconds.

For this project we will use the TeraAsic DE1-SOC Development board for demonstrating the vending machine. The development board has an Altera Cyclone FPGA that you will program with your hardware design. The board has a plethora of buttons, switches, LEDs, and displays that you will make use of. A clock signal is provided by an onboard oscillator circuit. Documentation of the board can be found at the following:

https://www.terasic.com.tw/cgi-bin/page/archive_download.pl?Language=China&No=836&FID=ae336c1d5103cac046279ed1568a8bc3

Grading

The project will be graded by demonstration on the provided FPGA board. In addition, all Verilog files must be submitted on CANVAS submission box.

Your top-level module MUST (spelling must match) have the following interface:

Input clk, reset;

Input [3:0] S3_0;

Input [3:0] S8_5;

Input B0, B1, B2, B3;

Output [7:0] display0, display1, display2, display3, display4, display5;

Aside from this interface, you are free to implement the design in whatever manner if you think is best. If you believe it is necessary to modify the specified interface, you must confirm with the instructor. Points will be deducted if your top-level module does not follow the specified interface.

Getting Started and Hints

First, start by drawing a state diagram for the operation of the vending machine. Second, draw a block diagram that illustrates the different submodules you plan to implement within your design and how those modules will interface with one another. You will receive 20 points to your final project grade for at least showing these diagrams by end of lab on Friday July 27th, 2018. The diagrams must be clear, and you must be able to explain it in detail to receive full credit.

We will have a hands-on lab session on Monday July 30th, 2018 during normal class hours. The purpose of this session is to get you started with using the FPGA boards. Until that session you are free to investigate the board on your own. Keep in mind you can begin to implement the design even before you have access to the board. In fact, you should verify the operation of your system in simulation completely before attempting to put your design on board.

Review the sections on decoding in the text to get an understanding of the operation of 7-segment displays. Implement a module that would be responsible for displaying characters/symbols on a single 7-segment display.

The vending machine tracks time in seconds and so it may be necessary to divide the incoming board clock frequency down to a more useful clock rate. There are plenty resources online for dividing clocks using Verilog.

The push buttons may require debouncing to prevent erroneous inputs being captured by your system. Investigate the causes and solutions to switch bounce.

https://www.allaboutcircuits.com/technical-articles/switch-bounce-how-to-deal-with-it/