We use Simulator paging-linear-translate.py to study how the address translation work with the linear paging table. We ran a configuration and got the following output with a slight modification. Please fill in the blanks. ARG address space size 16k ARG phys mem size 512k ARG page size 2k ARG verbose True ARG addresses -1 The format of the page table is simple: The high-order (left-most) bit is the VALID bit. If the bit is 1 , the rest of the entry is the PFN. If the bit is 0 , the page is not valid. Use verbose mode (v) if you want to print the VPN \# by each entry of the page table. down to the max size) Virtual Address Trace VA: 0x0000390e (decimal: 14606) VPN: PA