We use Vivado 2018.1 for this assignment. Please include any steps taken in Vivado to complete this.

1 Description (1) Design a 4-bit shift register with the following interface specification clock input clock signal syuchronous reset; clear state of synchronous reset; clear state of the register to all '0's input din(3:0) inputdata input input load when '1', load data din (3:0) in parallel; otherwise, load din(0) serially dout (3:0) output data output For this design, create a VHDL model with two different architectures as explained below (a) In one architecture, use a single process statement to describe the design. (b) In another architecture, use 4 proccss statements plus other nccessary statements to de- scribe the design Create a testbench to simulate both models to make sure they are correct (2) Answer the following question in writing. Suppose the frequency of an available clock is 200 MHz. How would you design a circuit that raises its output for one cycle in every second