We want to measure the performance of a processor with 32-bit address and 32-bit data bus and 32 GPRs for memory-register move instructions.

a) Draw the CPU internal organization of above processor computer by clearly indicating the bit width of all internal buses and registers.

b) Draw a flow diagram of the micro execution steps for following instruction: move R1, M[100+R2] (content of memory at location 100+R2 will be loaded into R1)

c) Assuming a 2 GHz clock frequency and memory access time of 10ns, compute the execution time of above instruction (all CPU internal operations are one clock-cycle)