we will simulate the execution of a CPU, The CPU will execute assembly instructions and will manage internal registers and a stack, and external memory. The following diagram provides an outline of the data structure layout of the CPU registers RO R1 R2 R3 R4 PC stack 27 28 29 CPU memory Not shown in this diagram is an array of instruction objects that represent the assembly code. This will be a fixed array of length 200 and will be created and initialized when the CPU is created and is passed a ileName The CPU will read in the file, parse each command line, create a corresponding instruction object, and store it into the instruction arrdy The following table lists the opcodes the CPU will support OP Code arg1 ar2 ADD arg3 Description Takes the contents of the two registers and puts the sum into the first register listed Takes the contents of the two registers and puts the product into the first register listed Stores the contents of the register in memory location Get the contents of the memory location and store it in the register Reg1 Reg 2 MULT Reg1 Reg2 STORE Reg1Memor Regl Memory EQU Reg1 Reg2 Reg3 Stores 1 in third register, Reg3, if the first two registers are equal otherwise it stores a 0 into Reg3 Push contents of the given register onto stack Pop the top of the stack into the given register Skip the number of instructions indicated in the register, note it can be a negative number Load the value into the given register Display the contents of the given register If register Reg1 is set to 1, skip the number of instructions specified in the second register, Reg2. Otherwise execute the next instruction. Note, this is different logic that we are used to -1, display registers, -2 display memory, 3 display stack, -4 all 3 Ends the program PUSH POP GOTO Regl ReglValue LOAD OUT IF Reg1 Reg2 DEBUG Value END we will simulate the execution of a CPU, The CPU will execute assembly instructions and will manage internal registers and a stack, and external memory. The following diagram provides an outline of the data structure layout of the CPU registers RO R1 R2 R3 R4 PC stack 27 28 29 CPU memory Not shown in this diagram is an array of instruction objects that represent the assembly code. This will be a fixed array of length 200 and will be created and initialized when the CPU is created and is passed a ileName The CPU will read in the file, parse each command line, create a corresponding instruction object, and store it into the instruction arrdy The following table lists the opcodes the CPU will support OP Code arg1 ar2 ADD arg3 Description Takes the contents of the two registers and puts the sum into the first register listed Takes the contents of the two registers and puts the product into the first register listed Stores the contents of the register in memory location Get the contents of the memory location and store it in the register Reg1 Reg 2 MULT Reg1 Reg2 STORE Reg1Memor Regl Memory EQU Reg1 Reg2 Reg3 Stores 1 in third register, Reg3, if the first two registers are equal otherwise it stores a 0 into Reg3 Push contents of the given register onto stack Pop the top of the stack into the given register Skip the number of instructions indicated in the register, note it can be a negative number Load the value into the given register Display the contents of the given register If register Reg1 is set to 1, skip the number of instructions specified in the second register, Reg2. Otherwise execute the next instruction. Note, this is different logic that we are used to -1, display registers, -2 display memory, 3 display stack, -4 all 3 Ends the program PUSH POP GOTO Regl ReglValue LOAD OUT IF Reg1 Reg2 DEBUG Value END
