We would like to design an 32-bit arithmetic and logic unit (ALU) that takes two inputs A and B and that performs the following operations depending on the values of a control signal C: 32-bit Arithmetic Operations: Control Signals C Operation 0001 A plus B 0010 Increment A by 1 0000 A minus B 0011 Decrement A by 1 Addition and subtraction is supposed to be done for twos complement numbers. 32-bit Multiplication Operation. Implement the multiplier described in Table 6-80 in the textbook, or in the last lecture (to be downloaded from Moodle). Control Signals C Operation 0100 A times B Multiplication is supposed to be done for unsigned numbers. 32-bit Comparison Operations Control Signals C Operation 0101 Minimum of A and B 0110 Maximum of A and B 0111 (Maximum of A and B) divided by 2 The comparison is to be done for twos complement numbers and you are supposed to implement it yourself, so do not use the built in > and < available for standard logic vectors. 32-bit Shift Operations Control Signals C Operation 1001 Circular right shift of A 1000 Circular left shift of A 1010 Right shift of A with feed in 0 1011 Left shift of A with feed in 0 1110 Right shift of A with MSB replication 1101 Left shift of A with LSB replication 1100 (Circular right shift of A) plus (Circular right shift of B) 1111 (Circular right shift of A) plus (Circular left shift of A) Each operation above should be executed using a separate entity with one enable signal. The control signals should be executed using a 4-to-16 decoder with Enable and asserted high at the output. For each ALU operation, only one output of the decoder is to be asserted.