We would like to run the following code(s) on the pipeline MIPS. Please show the values of all the control signals only in clock cycle 6 (you can find the figure in course lectures too Note that the first instruction is fetched in clock cycle 1 Also note that no forwarding is assumed and any data (real) hazards (i.e., RAW dependencies) are handled strictly by the compiler. This is to say, you may modify any of the streams in a) or b) as the compiler would, to render the code hazard free. a) add $1, $3, $5 and $10, $8, $3 le $4, 16(S3) sub $11, $2, $7 sx $2,1ee($6) b) AC $1, $3, $5 add $10, $8, $3 le $4, 16(S3) sub $11, $2, $4 sx $11,8 $8) Fill in the tables below and write the control signals for each case on the schemes (4.51 Solution