What is a control hazard in the context of pipelined computer architecture?

$q,$

An error caused by incorrect data being loaded from memory.

A situation where the machine's power control interferes with instruction execution.

A problem arising from arithmetic operations within the pipeline.

A delay caused by a branch instruction where the decision to take the branch is not known until later stages of the pipeline.

Question $62$

$1$ pts

Temporal locality suggests that if a data location is referenced:

It will likely be referenced again soon.

It will be moved to a lower level of the memory hierarchy.

It will not be referenced again.

It is stored permanently in the cache.