What is AAA in the Verilog code snippet that describes the given FSM$?$

The FSM has the states Zero and One. The starting state is Zero. It has inputs clk$,$ rst$,$ and a and output T$.$ At Zero, T $=0.$ At One, T $=1.$ There is a transition from Zero to Zero with the condition a $=0,$ Zero to One with the condition a $=1,$ One to One with the condition a $=1,$ and One to Zero with the condition a $=0.$