What is the VHDL testbench and its timing diagram simulation of the following VHDL code?

1 4 7 8 9 11 VHDL Design 2 library IEEE; 3 use IEEE.std_logic_1164.all; 5 entity elevator is 6 port SF, SD, L1, L2: in std_logic; E1, E2, D1, D2: out std_logic); 10 end elevator; 12 architecture elevator_arch of elevator is 13 begin El