What is the waveform of this code in VHDL ??

------------------------------------------------------------------------------- 

--

 

-- Title : fa

 

-- Design : fa

 

-- Author : markos

 

-- Company : MU

 

--

 

-------------------------------------------------------------------------------

 

--

 

-- File : c:My_Designsfafasrcfa.vhd

 

-- Generated : Fri Nov 6 19:49:09 2020

 

-- From : interface description file

 

-- By : Itf2Vhdl ver. 1.22

 

--

 

-------------------------------------------------------------------------------

 

--

 

-- Description :

 

--

 

-------------------------------------------------------------------------------

 

--{{ Section below this comment is automatically maintained

 

-- and may be overwritten

 

--{entity {fa} architecture {fa}}

 

library IEEE;

 

use IEEE.std_logic_1164.all;

 

entity fa is

 

port(

 

a : in STD_LOGIC;

 

b : in STD_LOGIC;

 

c : in STD_LOGIC;

 

sum : out STD_LOGIC;

 

carry : out STD_LOGIC

 

);

 

end fa;

 

--}} End of automatically maintained section

 

architecture fa of fa is

 

begin

 

-- enter your statements here --

 

sum <= a="" xor="" b="" xor="">

 

carry <= (a="" and="" b)="" or="" (b="" and="" c)="" or="" (c="" and="">

 

end fa;