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What kind of timing problems may occur like signal delay when testing out the sequential system and solutions can be done to fix it? relating
What kind of timing problems may occur like signal delay when testing out the sequential system and solutions can be done to fix it?
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State Table STATE PRESENT STATE INPUT NEXT STATE OUTPUT Q1 QOX Q2+ Q1+ Q0+ ZD 00 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0 0 We implement design using 3 No's of D Flip Flops, Hence use K-Map to derive D inputs We implement design using 3 No's of D Flip Flops, Hence use K-Map to derive D inputs 80100 01 ID 20% OLI 10 10 TTT Dz=QqQq+Q, X+Q2Q, Qo D1 = Q2Q, x+ Q2Q, X+Q, QoX x Qot QA00 OD 10 Q299 00 OD 1L 10 all 10 11 10 Do=X+QQ,+ QLQ , Qo ZI=QQ1 +Q Po We implement a Moore FSM base sequence detector to identify arrival of "010" or "110". The output ZD is set to logic 1 at first occurence of above "010" or "110" input and reset to lofic 0 and second occurence. Hence ZD keeps toggling with "010" or "110" arrival. ZD is logically XORed with input X to give output Z. When ZD = 1 then Z=X' When ZD = 0 then Z = X State graph is shown below We use binary state enoding SY Let so = Q2Q, Q = 000 SI = 001 S2 = 010 S3 = 011 S4 = 100 S5=101 S6=1 to S7 = III State Table STATE PRESENT STATE INPUT NEXT STATE OUTPUT Q1 QOX Q2+ Q1+ Q0+ ZD 00 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0 0 We implement design using 3 No's of D Flip Flops, Hence use K-Map to derive D inputs We implement design using 3 No's of D Flip Flops, Hence use K-Map to derive D inputs 80100 01 ID 20% OLI 10 10 TTT Dz=QqQq+Q, X+Q2Q, Qo D1 = Q2Q, x+ Q2Q, X+Q, QoX x Qot QA00 OD 10 Q299 00 OD 1L 10 all 10 11 10 Do=X+QQ,+ QLQ , Qo ZI=QQ1 +Q Po We implement a Moore FSM base sequence detector to identify arrival of "010" or "110". The output ZD is set to logic 1 at first occurence of above "010" or "110" input and reset to lofic 0 and second occurence. Hence ZD keeps toggling with "010" or "110" arrival. ZD is logically XORed with input X to give output Z. When ZD = 1 then Z=X' When ZD = 0 then Z = X State graph is shown below We use binary state enoding SY Let so = Q2Q, Q = 000 SI = 001 S2 = 010 S3 = 011 S4 = 100 S5=101 S6=1 to S7 =
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