What needs to be added to this circuit to help control which flip$-$flop will be

changed on the next active clock pulse?

A data bus to carry the data to the desired flip$-$flop for storage, and prevent

the data from reaching the others

A set of enable gates $($AND gates$)$ to enable the data to reach the correct

flip$-$flop and prevent it from reaching the others

An address input which would be used to enable the desired flip$-$flop for

storage while also disabling the others

A demultiplexer to route data to the desired flip$-$flop for storage and prevent

the data from reaching the others

A multiplexer to select the desired flip$-$flop for storage, while deselecting the

others