What to Turn In

For this lab project, submit the final gate$-$level RTL circuit schematic design that shows the design

of your single cycle datapath. The diagram can be a drawing from software or scanned image of

your drawing on paper or a photo of your drawing. It should be based your design from the

previous lab.

Also turn in all of your source code and the code that tests your implementations. For each

problem, all the source files and the project configuration files must be packed as a single zip file.

The goal is that I can unpack your zip file and type a single command, e$.$g$.,$ "make" to compile

your whole project. In your project report, please also describe your testing methodology. In

particular, describe the instruction sequence $($your ISA testbench$)$ that you use to test, whether you

make any changes to your Lab $1$ testbench, why the sequence will prove the correctness, and what

is the expected printout if everything runs correctly. Task $1$: Implement a multicycle version of the calculator. You only need to implement three instructions$---$load, add, and negate.

All the three instructions take $3$ stages, ID$,$ EXE and WB to finish. Each stage uses one cycle. All instructions will print some messages at the WB stage to verify the execution is done in the multicycle manner. Table $1$ describes what each instruction does at every stage. Your implementation must show that the three instructions are completed in three steps. In particular, it is unacceptable to finish all work in one cycle and then just wait for the displaying of result. In other words, there should be a clear demonstration of the inter$-$stage registers and how they work in sequence.

$\backslash$table$[[$Instruction$,$ID$,$EXE,WB$],[$Load$,\backslash$table$[[$Read the value$],[$from the$],[$instruction$],[$word$.]],\backslash$table$[[$Extend the value to$],[8-$bit.$]],\backslash$table$[[$Store the value$],[$to the$],[$destination$],[$register$.],[$Display the$],[$loaded value.$]]],[$Add$,\backslash$table$[[$Read two$],[$operands from$],[$registers$]],\backslash$table$[[$Calculate$],[$operand$1+$operand$00]],\backslash$table$[[$Store the value$],[$to the$],[$destination$],[$register$.],[$Display the$],[$result$.]]],[$Negate$,\backslash$table$[[$Read the$],[$operand$.]],\backslash$table$[[$Calculate $-],[$operand$0]],\backslash$table$[[$Store the value$],[$to the$]]]]($ USE VHDL Language for coding $)$