Which component does following Verilog module implements?

A$.$ Decoder

B$.$ Multiplexer

C$.$ Shift Register

D$.$ Multiplier

E$.$ Priority Encoder

timescale $1n\frac{s}{1}ns$

module component

$($

input wire $1$:$0$ a$,$

input $b.$

input $c.$

input reg $[3$:$0]x.$

output reg $[3$:$0]Y.$

input $z$

:

always $($posedge z$)$

begin

if $)==(2*b00$

$)==(2*b01)==(2*b10)==(2*b11)==(2*b01)==(2*b10)==(2*b11$