Which of the following is true for the two verilog codes above?

1. sum is equal to a XNOR b.
2. The testbench part runs for 40 nano seconds.
3. Gate design level is used in the code.

"timescale lns / Ips module ha (input a, b, output sum, carry); assign sum=a*b; assign carry=a&b; endmodule "timescale Ins / Ips module testbench(); rega, b; wire sum, carry; integer i; ha dt (.a(a), .b(b), .sum (sum), .carry (carry)); initial begin a=0; b=0; $monitor ("a=sOb b=30b sum=30b carry=f0b", a, b, sum, carry); for (i=0; i