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Which of the following statements is true regarding ADDW R 2 , # 0 xAFD? Which of the following statements is true regarding ADDW R

Which of the following statements is true regarding "ADDW R2, #0xAFD"?
Which of the following statements is true regarding "ADDW R2, #0xAFD"?
This instruction is valid, and when this instruction is executed, "0xAFD" will be sign-extended into "0xFFFFFAFD" because 0xAFD has a sign bit of 1.
This instruction is invalid because the destination register is missing, i.e., only operand1 and operand2 are provided and there is no info on t the sum should be written.
This instruction is valid, and after this instruction is executed, there is no update to any condition flags in APSR ([C],[V],[N], and [Z]).
This instruction is invalid because the immediate value #0xAFD is not a valid immediate value supported by ADDW.

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