Why doesn't my code load anything onto the registers.

module Control$\_$Circuit $($

input clk$,$

input rst$,$

input $[15$:$0]$ instruction,

output $[7$:$0]$ Rin,

output $[7$:$0]$ Rout,

output $[1$:$0]$ addSub

$)$;

wire $[3$:$0]$ current$\_$state;

wire $[3$:$0]$ next$\_$state;

reg $[3$:$0]$ state$\_$reg;

$//$ Instantiate Next$\_$State FSM

Next$\_$State fsm $($

$.$instruction$($instruction$),$

$.$current$\_$state$($current$\_$state$),$

$.$next$\_$state$($next$\_$state$)$

$)$;

$//$ Instantiate oneHot modules to generate Rin and Rout

oneHot rin$\_$gen $($

$.$select$($next$\_$state$),$

$.$out$($Rin$)$

$)$;

oneHot rout$\_$gen $($

$.$select$($current$\_$state$),$

$.$out$($Rout$)$

$)$;

$//$ Register to hold the current state

always @$($posedge clk or posedge rst$)$ begin

if $($rst$)$

state$\_$reg $<=4\text{'}$b$0000$; $//$ Initial state

else

state$\_$reg $<=$ next$\_$state;

end

assign current$\_$state $=$ state$\_$reg;

endmodule

module datapath $($clk$,$ rst$,$ instruction, enableRegistersin, enableRegistersout, bus, myWire, addSub$)$;

input clk$,$ rst;

input $[15$:$0]$ instruction;

input $[15$:$0]$ enableRegistersin;

input $[15$:$0]$ enableRegistersout;

input $[1$:$0]$ addSub;

output $[15$:$0]$ bus;

output $[15$:$0]$ myWire;

genvar i;

generate

for $($i $=0$; i $<8$; i $=$ i $+1)$ begin: registerGeneration

$//$ Register R$0-$R$7$

myreg regin$($

$.$clock$($clk$),$

$.$x$($bus$),$

$.$enable$($enableRegistersin$[$i$]),$

$.$y$($myWire$[$i$]),$

$.$rst$($rst$)$

$)$;

tristatebuffer regout$($

$.$a$($myWire$[$i$]),$

$.$enable$($enableRegistersout$[$i$]),$

$.$b$($bus$)$

$)$;

end

endgenerate

$//$ Register A

myreg regA $($

$.$clock$($clk$),$

$.$x$($bus$),$

$.$enable$($enableRegistersin$[8]),$

$.$y$($myWire$[8]),$

$.$rst$($rst$)$

$)$;

$//$ ALU

aLU alu $($

$.$a$($myWire$[8]),$

$.$b$($bus$),$

$.$addSub$($addSub$[1$:$0]),//$ Assuming the ALU takes opcode from instruction

$.$result$($myWire$[9])$

$)$;

$//$ Register G

myreg regG $($

$.$clock$($clk$),$

$.$x$($myWire$[9]),$

$.$enable$($enableRegistersin$[9]),$

$.$y$($myWire$[10]),$

$.$rst$($rst$)$

$)$;

$//$ Tristate buffer for RegG output

tristatebuffer regGout $($

$.$a$($myWire$[10]),$

$.$enable$($enableRegistersout$[10]),$

$.$b$($bus$)$

$)$;

endmodule

module Next$\_$State $($

input $[15$:$0]$ instruction,

input $[3$:$0]$ current$\_$state,

output reg $[3$:$0]$ next$\_$state

$)$;

always @$(*)$ begin

case $($current$\_$state$)$

$4\text{'}$b$0000$: begin

case $($instruction$[15$:$12])$

$4\text{'}$b$0000$: next$\_$state $=4\text{'}$b$0001$;

$4\text{'}$b$0001$: next$\_$state $=4\text{'}$b$0010$;

$4\text{'}$b$0010$: next$\_$state $=4\text{'}$b$0011$;

$4\text{'}$b$0011$: next$\_$state $=4\text{'}$b$0011$;

$4\text{'}$b$0100$: next$\_$state $=4\text{'}$b$0011$;

default: next$\_$state $=4\text{'}$b$0000$; $//$ default state if no match

endcase

end

$4\text{'}$b$0001$: next$\_$state $=4\text{'}$b$1000$;

$4\text{'}$b$1000$: next$\_$state $=4\text{'}$b$0000$;

$4\text{'}$b$0010$: next$\_$state $=4\text{'}$b$0000$;

$4\text{'}$b$0011$: next$\_$state $=4\text{'}$b$0100$;

$4\text{'}$b$0100$: next$\_$state $=4\text{'}$b$0101$;

$4\text{'}$b$0101$: next$\_$state $=4\text{'}$b$0000$;

default: next$\_$state $=4\text{'}$b$0000$; $//$ default state if no match

endcase

end

endmodule

module outputter $($

input $[3$:$0]$ state,

input $[15$:$0]$ instruction,

output reg $[15$:$0]$ Rin,

output reg $[15$:$0]$ Rout,

output reg $[1$:$0]$ addSub

$)$;

reg $[3$:$0]$ triReg, RegEnable;

$//$ Wires for oneHot module outputs

wire $[15$:$0]$ triStateWire, triRegEnableWire;

$//$ Instantiate oneHot modules

oneHot writeDemux $($

$.$select$($triReg$),$

$.$out$($triStateWire$)$

$)$;

oneHot readDemux $($

$.$select$($RegEnable$),$

$.$out$($triRegEnableWire$)$

$)$;

$//$ Assignments to the outputs

always @$($state or instruction$)$ begin

case$($state$)$

$4\text{'}$b$0001$: begin $//$ load $1$

triReg $=4\text{'}$b$0000$; $//$ No output enable in this state

RegEnable $=$ instruction$[11$:$8]$; $//$ Rxin enable

end

$4\text{'}$b$1000$: begin $//$ load $2$

triReg $=4\text{'}$b$1010$; $//$ Data triReg enable

RegEnable $=4\text{'}$b$0000$; $//$ No register enable in this state

end

$4\text{'}$b$0010$: begin $//$ move

triReg $=$ instruction$[7$:$4]$; $//$ Rxout

RegEnable $=$ instruction$[11$:$8]$; $//$ Ryin

end

$4\text{'}$b$0011$: begin $//$ add sub xor $1$

triReg $=$ instruction$[11$:$8]$; $//$ Rxout

RegEnable $=4\text{'}$b$1000$; $//$ Ain

end

$4\text{'}$b$0100$: begin $//$ add sub xor $2$

triReg $=$ instruction$[7$:$4]$; $//$ Ryout

RegEnable $=4\text{'}$b$1001$; $//$ Gin

if $($instruction$[15$:$12]==4\text{'}$b$0011)$

addSub $=2\text{'}$b$01$; $//$ sub

else if $($instruction$[15$:$12]==4\text{'}$b$0010)$

addSub $=2\text{'}$b$10$; $//$ xor

else

addSub $=2\text{'}$b$00$; $//$ add

end

$4\text{'}$b$0101$: begin $//$ add sub xor $3$

triReg $=4\text{'}$b$1001$; $//$ Gout

RegEnable $=$ instruction$[5$:$2]$; $//$ Ryin

addSu