Winter 2019 Homework 2 is not mark. Students are encouraged to do the homework to be prepared for the quiz and examinations. A 10-minute Quiz (Quiz 2) will take place Wednesday, February 6th, 2:45 pm in class. The quiz will consist of a selection from the following. EXERCISE 1 Refer to the figures on page 2 and 3 to complete the following table Data Width Bus (n) Address Bus Width (k) Capacity (C) 16 16 32 32 16 16 24 24 32 EXERCISE 2 The following table presents different cache memories. The address bus is 32 bits wide. Fill the table with appropriate values. Leave blank when field does not apply Nb Sets Nb bytes Byte Addr Width Size Type per blockTag Width Set/Group Width 128 kB 128 kB 128 kB 128 kB 256 kB 256 kB 256 kB 256 kB Fully Associive N/A Direct MappedN/A Set Associative Set Associative Fully AssoctiveN/A Direct MappedN/A Set Associative2-way Set Associative 16 16 16 32 16 16 16 32 2-way 4-way 4-way