With reference to the architecture 5 stages pipeline described in Unit 3 as given as following: Instruction Fetch Instruction Decode Instruction Execution Memory Access Register The conceptual processor supports the instruction set as given in unit 3 . (a) According to the diagram of the five stages pipeline processor, analysis the concept processor is a CISC or RISC architecture? Why? (4 marks) (c) Modify the diagram given, explain how it can support register-memory instruction given in (a). Hint: You don't need to copy and redraw the whole diagram, and you only need to indicate the area of change. (8 marks)