Write a dataflow-style Verilog module corresponding to the full-adder circuit in Figure 8-1. Then instantiate multiple copies of it to create a structural Verilog model for a 4-bit ripple adder using the structure of Figure 8-2.

Please do this using verilog

full adder CIN CIN COUT COUT COUT CIN a3 b3 a2 b2 C. CINCOUT CIN S3 S2