Write a Verilog model that instantiates four copies of this circuit and connects C1 and C0 of the first instance to 11, C1+ and C0+ of the first instance to C1 and C0 of the 2nd instance, C1+ and C0+ of the 2nd instance to C1 and C0 of the 3rd instance, and C1+ and C0+ of the 3rd instance to C1 and C0 of the 4th instance

Consider the combinational circuit given below which has three inputs C1, CO, and X three outputs Cl+, CO+ and Y: C1+ 1 CO+ CO