Write a Verilog/SystemVerilog program using Icarus Verilog to calculate a 32 bit vector in IEEE 754 single precision format from two decimal integer, one to the left of the decimal point, and one to the right of the decimal point. The program does not need to by synthesizable which means language constructs may be used which do not have an equivalent Boolean logic equivalent. To assist with the conversion program, pay extra attention to the Verilog built-in functions which start with a $, such as $display(). You may use any Verilog / SystemVerilog variable type, but the output needs to be a 32 bit reg value in IEEE 754 single precision format. Using the program, convert the following values into IEEE 754 singe precision format:

1. 34.25

2. -234.75

3. 99.78

4. -678.45

5. 867.5309

Result:

Use the format on the following page to document and turn in your program and execution results as a pdf file.

Hints: Search for Icarus Verilog and GTKWave on the internet. You should be able to find a Linux, MacOS, and Windows version of the open source software. Below is an example snippet of Verilog code to help you get started.

The linux command line compile for iverilog (Icarus Verilog) uses the following commands to execute:

iverilog o float_test float_test.v ./float_test

module float_test;

reg [31:0] lhs; // Left had side of the decimal number.

reg [31:0] rhs; // Right hand side of the decimal number.

reg [31:0] res; // Resulting IEEE 754 value initial begin

lhs = 32d34;

rhs = 32d56;

// Place your calculations here

// Print the result something like:

$display(%d\.%d = %b %b %b, lhs, rhs, res[31], res[30:23], res[22:0]);

end

endmodule