write a VHDL program consisting of a single entity whose architecture is a single process that implements a CNOT (controlled NOT) gate, which is the same as an XOR gate.

inputs. outputs a_in b_in. cnot_out 0. 0. 0 0. 1. 1 1. 0. 1 1. 1. 0

use exactly the names given above for the signals. All your signals should be of type bit (NOT integer)