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//------------------------------------------------------------------------- //RX control block receives data from serial RXIN port, 1 bit per clock //aggregates the bits into a byte based on uart protocol //Writes the aggregated byte onto a register and sends out an interrupt pulse //------------------------------------------------------------------------- module veri_uart_rxctrl ( input CLK , input RSTB , input RXD , output [7:0] REGWRDAT, output REGWR ); //------------------------------------------------------------------------- //------------------------------------------------------------------------- parameter ST_IDLE = 0, ST_GETRX = 1, ST_STOPB = 2; //------------------------------------------------------------------------- //------------------------------------------------------------------------- reg regwr_s, regwr_r ; reg ldda_s ; reg[3:0] dcnt_s, dcnt_r ; reg[1:0] st_x_s, st_x_r ; reg[7:0] tmpdat_r, tmpdat_s ; //------------------------------------------------------------------------- //rxin state machine has 3 states. //------------------------------------------------------------------------- always @* begin regwr_s = 1'b0 ; st_x_s = st_x_r ; dcnt_s = dcnt_r ; ldda_s = 1'b0 ; tmpdat_s = tmpdat_r ;

case(st_x_r) ST_IDLE: begin dcnt_s = 4'b0111 ; tmpdat_s = 8'h00; if(!RXD) begin st_x_s = ST_GETRX ; end end ST_GETRX: begin ldda_s = 1'b1 ; dcnt_s = dcnt_r - 1 ; tmpdat_s[dcnt_r -: 1] = RXD ; if(dcnt_r == 4'h0)begin st_x_s = ST_STOPB ; regwr_s = 1'b1 ; dcnt_s = 4'b0000; end end ST_STOPB: begin dcnt_s = dcnt_r + 1 ; if(dcnt_r == 4'h1)begin dcnt_s = 4'h0; st_x_s = ST_IDLE ; end end endcase end //------------------------------------------------------------------------- //register control signals & data //------------------------------------------------------------------------- always @(posedge CLK or negedge RSTB) begin if(!RSTB) begin st_x_r <= ST_IDLE ; regwr_r <= 1'b0 ; dcnt_s <= 4'h0 ; end else begin st_x_r <= st_x_s ; regwr_r <= regwr_s ; dcnt_r <= dcnt_s ; end end

always @(posedge CLK) begin if(ldda_s) tmpdat_r <= tmpdat_s ; end //------------------------------------------------------------------------- //Output assignments //-------------------------------------------------------------------------

assign REGWR = regwr_r ; assign REGWRDAT = {tmpdat_r[7:0]} ; //-------------------------------------------------------------------------

endmodule //-------------------------------------------------------------------------