Write the above diagram as a Verilog program using structure methods with D flip-flops. That is, do not use a register, use an array of D flip flop modules. The test bench should demonstrate transitions such that every vertex in the state machine is visited at least twice for the same input sequence. This includes having the reset and the clock working correctly in sequence.

x=0 0 01 y=0 x=0,y = 0 0 1 10 x=1,y=