Write the SystemVerilog HDL language for the problem and provide the code typed out not handwritten.

4. Design a modified priority encoder that receives an 8-bit input, A7:0 and produces a 3-bit output, Y2:0. Y indicates the most significant bit of the input that is TRUE. Y should be 0 if none of the inputs are TRUE. 4. Design a modified priority encoder that receives an 8-bit input, A7:0 and produces a 3-bit output, Y2:0. Y indicates the most significant bit of the input that is TRUE. Y should be 0 if none of the inputs are TRUE