Write the VHDL code for eight register modules that will be part of a register file consisting of a 3 to 8 decoder, eight register modules, and two 8 to 1 MUX. Inputs to register file are wr(3 bit)(write to register), in(16 bits), clock, reset(asynchronous), rd1 and rd2(3 bits)(selects registers to read from) and wre(write enable). Outputs are outA and outB (16 bits)