Write Verilog code and testbench to create a left aligned 8-bit pulse width modulation (PWM) module. The PWM module will have clock input and a PWM output line (1-bit) along with a counter register (8-bit), a period register (8-bit), and a compare register (8-bit). Given that this module performs math, it will need a reset input to initialize all registers to zero. Additionally, the PMW module will need a way to write to the period and compare registers from the testbench.

For this, equip your PWM module with two 8-bit busses that will be used to write values to these two registers from the testbench. The testbench must drive the clock line at a frequency of 1 MHz. Test the period register functionality with the following values: 0x7F, 0xFF. Use the following values to test the compare register with both of the period register values previously specified: 0x1F, 0x3F, and 0x7F.

Comment your code and testbench thoroughly. Show simulation of the testbench