Write verilog model for following state machine.

The states are: $S1,S2,S3,S4,S5,S6,S7,$ and $S8.$

The input values are $\{00,01,10,11\}.$

Output values are: $\{00,01,10,11\}.$

The initial state is $S1($when $r$ st is made $1).$