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writing the code for project for the train collision avoidance system using Verilog HDL based on this explanation and its priority E S>P S>G E>P

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writing the code for project for the train collision avoidance system using Verilog HDL based on this explanation and its priority
E S>P S>G E>P E>G P>G Description Superfast is given priority Superfast is given priority Superfast is given priority> Express is given priority Express is given priority Passenger is given priority Different combinations of trains 2.2 Theoretical explanation Below table 2 showing some binary values, here 0000 denotes no train is coming and any other binary value other say 0001, 01000, 1000 denote that a train of particular type is coming. Table 2: Priority of the Trains Left Side Right Side Left Side Right Side Status Stop Trains Trains Status Status Gate 0000 0001 0 1 1 0100 0000 1 0 1 0010 0001 1 0 1 1000 1000 1 0 0 1 0 Case 1: There is train on right side i.e. here 0001 say superfast so we check for left side since there is no train, gates are open for both the trains as from the given algorithm Case 2: There is train on left side i.e. here 0100 say passenger so algorithm checks for right side since there is no train gates are open for both the trains as from the given algorithm Case 3: When there are trains on both sides say express on left and goods on right so from Table (1) priority is given to left side train. Case 4: When there are trains with equal priority on both sides then we assume left train is given highest priority from Table (1)

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