You are designing a 2-bit adder from two full adders. The adder has input and output registers and must complete the addition in one clock cycle. The design for the adder is shown below. CLK CLK out out Each full adder has the following propagation delays: C-in to C-out: 20 ps . C_in to S (sum): 20 ps .A, B to Cout: 25 ps .A, B to S (sum): 30 ps Each full adder has the following contamination delays: . C_in to either output: 15 ps . A, B or either output: 22 ps Each flip-flop has the following characteristics: . setup time: 30 ps . hold time: 10 ps . propagation delay: 25 ps . contamination delay: 11 ps How much clock skew can the circuit tolerate if it must operate at 8 GHz without causing a setup or a hold time violation? Select one: O a. 15 O b. 25 O d. 16