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You are given a 2 4 MB 3 - way associative cache that has 1 0 2 4 B cache lines ( A cache line

You are given a 24 MB 3-way associative cache that has 1024 B cache lines (A cache line is also called a cache block). The system has 32-bit physical memory addresses, with bits numbered from 0(least significant) to 31(most significant). What bit ranges are associated with each of the offset, index, and tag fields of an address? Fill in the blanks here, and show your work in the next problem. Remember (from the exam directions) that bit ranges are inclusive on both ends. Tag most significant bit (MSB): Tag least significant bit (LSB): Index MSB: Index LSB: Offset MSB: Offset LSB:

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