You are given designs of 3 caches for a 16-?bit address machine:

D1: Direct-?mapped cache.

Each cache line is 1 byte.

10-?bit index, 6-?bit tag. 1 cycle hit time.

D2:

2-?way set associative cache. Each cache line is 1 word (4 bytes).

7-?bit index, 7-?bit tag. 2 cycle hit time.

D3: fully associative cache with 256 cache lines.

Each cache line is 1 word. 14-?bit tag. 5 cycle hit time.

Answer the following set of questions: a) What is the size of each cache? b) How much space does each cache need to store tags? c) Which cache design has the most conflict misses? Which has the least? d) The following information is given to you: hit rate for the 3 caches is 50%, 70% and 90% but did not tell you which hit rate corresponds to which cache, which cache would you guess corresponded to which hit rate? Why? e) Assuming the miss time for each is 20 cycles, what is the average service time for each? (Service Time = (hit rate)*(hit time) + (miss rate)*(miss time)).

Question 2 . Assume we have a computer where the CPI is 1.0 when all memory accesses (including data and instruction accesses) hit in the cache. The cache is a unified (data + instruction) cache of size 256 KB, 4-?way set associative, with a block size of 64 bytes. The data accesses (loads and stores) constitute 50% of the instructions. The unified cache has a miss penalty of 25 clock cycles and a miss rate of 2%. Assume 32-?bit instruction and data addresses. Now, answer the following questions:

a) What is the tag size for the cache? b. How much faster would the computer be if all memory accesses were cache hits?