You are tasked to manually implement the following Verilog module in an FPGA, using the CLBs given below. module func1(output [2:0] c, input (1:0] A, B, input clk); reg temp1 (1:0]; assign C[2] = A[1] & B[1]; assign C[1:0] = temp1; always @(posedge clk) temp1