You are the chief architect at a major processor manufacturing company. You are in charge of extending the current ISA for a new line of processors targeted primarily for multimedia applications. You are considering adding a fused multiply/add instruction to the ISA. The semantics of the instruction is given as d = a + b c, where the values a, b, c, and d all reside in registers. The advantage of this new instruction is that by merging adds and multiplies it can reduce the overall instruction count. The actual reduction will depend on the number of fusible adds and multiplications present in the application. The disadvantage is that its implementation requires extending the clock cycle time by 10% and increases the CPI by 15%.

(a) Assuming 32-bit instructions and 32 registers in the ISA show the binary encoding for the fused multiply-add instruction. Explain the use of each field. Discuss potential pitfalls.

(b) Under what conditions does adding this instruction to the ISA lead to an overall performance increase (show calculation)?

(c) If we are using MIPS (millions of insts/sec) as a metric for system performance, what impact would the above change have on that metric? (You can give a qualitative answer).

(d) Are there other issues to be considered in implementing this instruction?