You are the human compiler for a VLIW machine whoe specifications are as follows:

There are $3$ fully pipelined functional units $($ALU$,$ MU and FPU$).$

Integer Arithmetic Logic Unit $($ALU$)$ has a $1-$cycle latency.

Memory Unit $($MU$)$ has a $2-$cycle latency.

Floating Point Unit $($FPU$)$ has a $3-$cycle latency, and can perform either FADD or FMUL $($floating point add $/$ floating point multiply$)$ on floating point registers.

This machine has only $4$ integer registers $($r$1..$ r$4)$ and $4$ floating point registers $($f$1..$ f$4)$

The machine does not implement hardware interlocking or data forwarding.

For the given assembly code, fill Table $1$ with the appropriate VLIW instructions. Provide the VLIW instructions that lead to the best performance. Use the minimum number of VLIW instructions, show the NOP instructions you may need to insert.

#INSTRUCTIONS ILLUSTRATION ###################################

#LD LOAD FROM MEMORY # LD LOAD$\_$REGISTER, OFFSET$\_$VALUE, ADDRESS

#FMUL MULTPLY FLOAT # FMUL RESULT$\_$REGISTER, OPERAND$\_$REG$1,$ OPERAND$\_$REG$2$

#FADD ADD FLOAT # FADD RESULT$\_$REGISTER, OPERAND$\_$REG$1,$ OPERAND$\_$REG$2$

#ADDI ADD IMMEDIATE # ADDI RESULT$\_$REGISTER, OPERAND$\_$REG$1,$ VALUE

#ST STORE TO MEMORY # ST STORE$\_$R$$GISTER$,$ OFFSET$\_$VALUE, ADDRESS

############################################################################

#CODE BEGINS :

LD $fl,0,(r1)$

LD $f2,0($r$2)$

FMUL $f1,f1,f1$

FADD $f1,f1,f2$

ADDI $r3,r3,4$

ST f$1,-4($r$3)$

ADDI $r1,r1,4$

ADDI $,r2,r2,4$

$\backslash$table$[[$VLIW Instruction,ALU,MU$,$FPU$],[,,,],[,,,],[,,,],[,,,],[,,,],[,,,],[,,,],[,,,],[,,,],[,,,]]$