You are to design a 2-bit CLA adder. Follow the steps below but make sure you read the entire assignment before you start. Refer to Chapter 2 for examples of behavioual and structural circuit models. 1. Bahaviroal models: Design a 2-bit CLA adder as follows CLA is discussed in Chapter 3. Create a Verilog model for a 2-bit CLA and use assign statements to enter SOP Boolean expressions for 2-bit bit-wise PGU and sum unit (SU). Also use assign and enter POS Boolean expression for c0 and SOP expression for c1 of a 2-bit CGU. 2. Testbench: Create a testbench file to test your 2-bit CLA using the following four test cases. a = 2b10 b = 2b10 cin = 1b0 a = 2b01 b = 2b10 cin = 1b1 a = 2b11 b = 2b01 cin = 1b0 a = 2b11 b = 2b01 cin = 1b0 Refer to the textbook to create a Verilog tester module and enter the above test cases as test vectors. Note, you must simulate to get outputs from your Verilog model.