You are trying to appreciate how important the principle of

locality is in justifying the use of a cache memory, so you experiment with a

computer having an L$1$ data cache and a main memory $($you exclusively focus on

data accesses$).$ The latencies $($in CPU cycles$)$ of the different kinds of accesses

are as follows: cache hit, $1$ cycle; cache miss, $105$ cycles; main memory access

with cache disabled, $100$ cycles.

When you run a program with an overall miss rate of $5\%,$ what

will the average memory access time $($in CPU cycles$)$ be$?$