$***$you can do the second part in c

Background

Basic Computer Model $-$ Von Neumann Model

Von Neumann computer systems contain three main building blocks: the central processing unit $($CPU$),$ memory, and input$/$output devices $($I$/$O$).$ These three components are connected together using the system bus. The most prominent items within the CPU are the registers: they can be manipulated directly by a computer program, See figure one:

Function of the Von Neumann Component:

Memory: Storage of information $($data$/$program$)$

Processing Unit: Computation$/$Processing of Information

Input: Means of getting information into the computer. e$.$g$.$ keyboard, mouse

Output: Means of getting information out of the computer. e$.$g$.$ printer, monitor

Control Unit: Makes sure that all the other parts perform their tasks correctly and at the correct time.

General Registers:

The number of registers in a processor unit may vary from one processor to another. Below are the general registers used by most processor:

One of the CPU registers is called as an accumulator $AC$ or $\text{'}$A$\text{'}$ register. It is the main operand register of the ALU. it is used to store the result generated by ALU.

The data register $($MDR$)$ acts as a buffer between the CPU and main memory. It is used as an input operand register with the accumulator.

The instruction register $($IR$)$ holds the opcode of the current instruction.

The address register $($MAR$)$ holds the address of the memory in which the operand resides.

The program counter $(PC)$ holds the address of the next instruction to be fetched for execution.

Additional addressable registers can be provided for storing operands and address. This can be viewed as replacing the single accumulator by a set of registers. If the registers are used for many purpose, the resulting computer is said to have general register organization. In the case of processor registers, a registers is selected by the multiplexers that form the buses.

Communication Between Memory processing Unit

Communication between memory and processing unit consists of two registers:

Memory Address Register $($MAR$).$

Memory Data Register $($MDR$).$

To read,

The address of the location is put in MAR.

The memory is enabled for a read.

The value is put in MDR by the memory.

To write,

The address of the location is put in MAR.

The data is put in MDR$.$

The Write Enable signal is asserted.

The value in MDR is written to the location specified.

Generic CPU Instruction Cvcle

The generic instruction cycle for an unspecified CPU consists of the following stages:

Fetch instruction: Read instruction code from address in PC and place in IR$.($ IRlarrMemory$[PC]$

Decode instruction: Hardware determines what the opcode$/$function is$,$ and determines which registers or memory addresses contain the operands.

Fetch operands from memory if necessary: If any operands are memory addresses, initiate memory read cycles to read them into CPU registers. If an operand is in memory, not a register, then the memory address of the operand is known as the effective address, or EA for short. The fetching of an operand can therefore be denoted as Register larr Memory $[$EA$].$ On today's computers, CPUs are much faster than memory, so operand fetching usually takes multiple CPU clock cycles to complete.

Execute: Perform the function of the instruction. If arithmetic or logic instruction, utilize the ALU circuits to carry out the operation on data in registers. This is the only stage of the instruction cycle that is useful from the perspective of the end user. Everything else is overhead required to make the execute stage happen. One of the major goals of CPU design is to eliminate overhead, and spend a higher percentage of the time in the execute stage. Details on how this is achieved is a topic for a hardware$-$focused course in computer architecture.

Store result in memory if necessary: If destination is a memory address, initiate a memory write cycle to transfer the result from the CPU to memory. Depending on the situation, the CPU may or may not have to wait until this

Below is an example of a full instruction cycle which uses memory addresses for all three operands.

mull $x,y,$ product

Fetch the instruction code from Memory$[$PC$]$

Decode the instruction. This reveals that it's a multiply instruction, and that the operands are memory locations $x,y,$ and product.

Fetch $x$ and $y$ from memory.

Multiply $x$ and $y,$ storing the result in a CPU register.

Save the result from the CPU to memory location product.

Addressing Modes

The term addressing modes refers to the way in which the operand of an instruction is specified. Information contained in the instruction code is the value of the operand or the address of the result$/$operand$.$ Following are the main addressing m