You can use any MOS process you want. OVDD VGEMA Vo -0+ M1 M3 M2 Design specs: 1) Vo=Vi=Vpp/2 (DC) 2) vo/vi=1 (ac) Report should include 1) DC, ac and frequency analysis done by hand. Through any simulation program (LT Spice, Cadence, etc) 2) Investigation of DC performance of the circuit, showing that Vo=Vi at DC. 3) Investigation of ac performance of the circuit, a) showing that vo/vi=1 at ac, b) showing the cut-off frequency value of the circuit, C) showing the poles and zeros of the transfer function, d) showing the phase behavior. 4) Investigation of the transient response for a sinusoidal signal (1MHz, 1V) at the input, showing the distortion at the output. Add a feedback resistor of 10k between Gate3 and Drain3. Then, repeat all things in the simulation part (design specs may change). Interpret the simulation results. You can use any MOS process you want. OVDD VGEMA Vo -0+ M1 M3 M2 Design specs: 1) Vo=Vi=Vpp/2 (DC) 2) vo/vi=1 (ac) Report should include 1) DC, ac and frequency analysis done by hand. Through any simulation program (LT Spice, Cadence, etc) 2) Investigation of DC performance of the circuit, showing that Vo=Vi at DC. 3) Investigation of ac performance of the circuit, a) showing that vo/vi=1 at ac, b) showing the cut-off frequency value of the circuit, C) showing the poles and zeros of the transfer function, d) showing the phase behavior. 4) Investigation of the transient response for a sinusoidal signal (1MHz, 1V) at the input, showing the distortion at the output. Add a feedback resistor of 10k between Gate3 and Drain3. Then, repeat all things in the simulation part (design specs may change). Interpret the simulation results